1. Field of the Invention
The present invention relates generally to an analog switching circuit having a plurality of MOS transistors, and more particularly to an analog switching circuit comprising a gate potential control circuit as well as a substrate potential setting circuit. The switching circuit of the present invention is, for example, applied to a CMOS analog switching circuit or a circuit having the CMOS analog switching circuit.
2. Description of the Related Art
2.1. Previously Proposed Art:
A conventional complementary metal-oxide-semiconductor (CMOS) analog switching circuit is shown in FIG. 1.
As shown in FIG. 1, a conventional CMOS analog switching circuit 701 has a pair of p-channel MOS (PMOS) transistor Q110 and n-channel MOS (NMOS) transistor Q120 functioning as a CMOS analog switch, and the transistors Q110 and Q120 respectively function as a transfer gate. A control signal transmitted through a control terminal G is converted and amplified by a first converting buffer INV11. The control signal converted is input to a base of the PMOS transistor Q110. Also, the control signal converted is again converted and amplified by a second converting buffer INV12, and the control signal converted by the second converting buffer INV12 is input to a base of the NMOS transistor Q120. This conventional CMOS analog switching circuit 701 is well-known.
When a surge pulse having a positive voltage is applied to an input terminal IN, a lateral p-n-p bipolar transistor in which an n-type semiconductor substrate (or an n-type well region) placed just under the PMOS transistor Q110 functions as a base, a p-type region functioning as an input side main electrode of the PMOS transistor Q110 functions as an emitter and a p-type region functioning as an output side main electrode of the PMOS transistor Q110 functions as a collector is formed as a lateral p-n-p parasitic transistor Ty. Therefore, even though the transistors Q110 and Q120 are turned off to turn off the CMOS analog switching circuit 701, the positive surge is transmitted to an output terminal OUT of the CMOS analog switching circuit 701 through the parasitic transistor Ty, and an electric potential at the output terminal OUT is changed as a result of an influence of the positive surge.
In the same manner, when a surge pulse having a negative voltage is input to the input terminal IN, a lateral n-p-n bipolar transistor in which an p-type well placed just under the NMOS transistor Q120 functions as a base, an n-type region functioning as an input side main electrode of the NMOS transistor Q120 functions as an emitter and an n-type region functioning as an output side main electrode of the NMOS transistor Q120 functions as a collector is formed as a lateral n-p-n parasitic transistor Tx. Therefore, even though the transistors Q110 and Q120 are turned off to turn off the CMOS analog switching circuit 701, the negative surge is transmitted to the output terminal OUT through the parasitic transistor Tx, and an electric potential at the output terminal OUT is changed as a result of an influence of the negative surge.
FIG. 2 shows another conventional CMOS analog switching circuit.
As shown in FIG. 2, a conventional CMOS analog switching circuit 702 has the transistors Q110 and Q120 and a deformed MOS inverter 703 composed of a loading device and a driver device arranged between the input terminal IN and a grounded electric potential terminal Vss. The loading device is composed of a pair of NMOS transistor Q130 and PMOS transistor Q140 functioning as a CMOS transfer gate (or an analog switch). The driver device is formed by an NMOS transistor Q150 of which a source is grounded. In the deformed MOS inverter 703, when an electric potential at the control terminal G is set to a high level, the transistors Q120, Q130 and Q140 are turned on. Therefore, an input signal passing through the input terminal IN is transmitted to the p-type well of the NMOS transistor Q120 through the transistors Q130 and Q140. That is, an electric potential of the p-type well of the NMOS transistor Q120 changes with an electric potential of the input signal. Therefore, a channel conductance demodulating effect of the NMOS transistor Q120 caused by the change of the electric potential of the input signal is reduced, and an on-state characteristic of the NMOS transistor Q120 is improved.
However, in the conventional CMOS analog switching circuit 702, when a positive surge is input to the input terminal IN, the positive surge still influences on the output terminal OUT through the parasitic transistor Ty in the same manner as in the conventional CMOS analog switching circuit 701.
To solve the adverse influence of the positive surge and the negative surge, an analog switching circuit is disclosed in the Published Unexamined Japanese Patent Application No. H6-103733 of 1994. In this analog switching circuit, a first-stage CMOS analog switch integrated in a first-stage semiconductor region and a second-stage CMOS analog switch integrated in a second-stage semiconductor region are connected with each other in series on a semiconductor substrate, and a charge absorbing region having a conductive type opposite to that of the semiconductor substrate is formed on a surface of the semiconductor substrate along a boundary portion between the first-stage semiconductor region and the second-stage semiconductor region. In the above configuration, when a surge pulse is input to an input terminal of the first-stage CMOS analog switch, a p-n junction between the charge absorbing region connected with the input terminal of the first-stage CMOS analog switch and the semiconductor substrate is formed on the surface of the semiconductor substrate, and the p-n junction is set in a forward bias condition. Therefore, even though minority carriers are injected from the charge absorbing region to the semiconductor substrate, the influence of the minority carriers on an output terminal of the second-stage CMOS analog switch can be removed.
2.2. Problems to be Solved by the Invention:
However, because the first-stage CMOS analog switch (or a transfer gate) and the second-stage CMOS analog switch (or another transfer gate) are connected with each other in series, operational delays of the analog switches occur in series, and a delay of an output signal is increased. In particular, because an electric power accumulated in a parasitic capacitor which is generated at a connecting point of the analog switches is discharged through a channel resistor of the first-stage CMOS analog switch and an output resistor of an external amplifier connected with the first-stage CMOS analog switch, a signal transmission delay and a signal waveform distortion (or a high-frequency attenuation) depending on a CR time constant determined by a parasitic capacitance C of the parasitic capacitor and a resistance R of the channel resistor occur in the analog switches (or transfer switches).
Also, when a sum of two resistances (called on-state resistances) of the analog switches arranged in series in a condition that the analog switches are turned on is equalized with an on-state resistance of an analog switching circuit in which a single analog switch is only arranged, it is required to widen an area of each of the analog switches twice. As a result, there is a drawback that a chip area required for the analog switches arranged in series becomes four times as wide as that for an analog switching circuit in which a single analog switch is only arranged.
Further more, a threshold value of NMOS transistor Q120 is not constant due to manufacturing errors. When the threshold value of NMOS transistor Q120 is extremely low, a problem arises. That is, if a substrate region potential of the NMOS transistor Q120 is reduced in response to a negative surge pulse, there is a possibility that the NMOS transistor Q120 may be turned on erroneously due to a potential difference between the gate potential and the substrate (or well) region potential.